Technological advances in integrated circuit (IC) materials and design have produced ICs with smaller and more complex features. With the shrinking technology nodes, integrated circuit manufacturing has realized many challenges. One such challenge is the topographical issues that arise when features of different aspect ratios are closely arranged on a substrate. For example, device designs may require forming a layer of material in a plurality of trenches having different aspect ratios. However, maintaining uniformity and/or control of the material formed in the trenches may be difficult to due to micro-loading effects. For example, an etching process has a different etch rate in different dimensions. Therefore, a wider trench may have a different etch property than a narrow trench. Thus, applying a similar process recipe can provide different results depending on the topography. This can lead to poor uniformity across the substrate. For example, despite being processed simultaneously, the thickness of a material disposed in a wide trench and an adjacent narrow trench may differ by thousands of Angstroms.
Thus, it is desirable to have an improved method of forming a layer of a semiconductor device, where the layer is formed on a substrate having a plurality of features (e.g., trenches) of varying dimensions.